As semiconductor devices scale to smaller dimensions, the ability to harness device improvements with decreased size becomes more challenging. The synthesis of three-dimensional semiconductor transistors, such as fin type field effect transistors (finFET), involves challenging overlay and contact issues. For example, known FinFET based logic design rules do not allow placing gate contact over an active fin region, because an electrical short to source/drain (S/D) may arise. This prohibition in gate contact arrangement incurs a scaling penalty of approximately 10% because of additional area entailed in gate contact placement to avoid the S/D region.
With respect to these and other considerations, the present disclosure is provided.